---
title: Accuracy-Enhanced Hybrid Temporal Computing
url: https://www.emergentmind.com/topics/accuracy-enhanced-hybrid-temporal-computing-e-htc
type: topic
---

# Accuracy-Enhanced Hybrid Temporal Computing

Accuracy-Enhanced Hybrid Temporal Computing (E-HTC) is a framework for ultra-low-power hardware accelerators with deterministic additions. It extends Hybrid Temporal Computing (HTC), which leverages pulse-rate and temporal data encoding to reduce switching activity and energy consumption but loses accuracy due to its multiplexer (MUX)-based scaled addition. E-HTC introduces two bitstream addition schemes—an Exact Multiple-input Binary Accumulator (EMBA) and a Deterministic Threshold-based Scaled Adder (DTSA)—and integrates them into a multiplier accumulator (MAC) unit that supports both unipolar and bipolar encodings. The framework is validated through a Finite Impulse Response (FIR) filter and an 8-point Discrete Cosine Transform (DCT)/iDCT engine, with reported gains in RMSE and PSNR together with reductions in area and power relative to MUX-based HTC and Counter-Based Stochastic Computing (CBSC) baselines [2509.22999].

## 1. Origins in hybrid temporal arithmetic

The antecedent HTC framework was introduced as a hardware-acceleration method that combines two temporal data encoding schemes: temporal encoding, or race logic, in which data is represented as the arrival time of a single pulse, and pulse-rate encoding, in which data is represented as the number of pulses within a time window. Its stated objective was ultra-low energy arithmetic with reduced switching activity while remaining general enough to implement multiplication, addition, and MAC operations [2407.08975].

This design lineage is connected to earlier temporal-computing work on race logic, where information is encoded in the timing of digital edges rather than in Boolean levels. That literature associated race logic with tropical algebra and used temporal memory to partition feed-forward computations into stages organized as a state machine, thereby broadening the expressibility of time-coded computation beyond ad hoc circuit mappings [2009.14243].

Within this context, E-HTC addresses a specific limitation of the original HTC formulation. The 2024 HTC framework reported that, relative to CBSC, the HTC MAC reduced power consumption by $45.2\%$ and area footprint by $50.13\%$; the HTC-based FIR filter reduced power consumption by $36.61\%$ and area cost by $45.85\%$; and the HTC-based DCT filter consumed $23.34\%$ less power and occupied $18.20\%$ less area than the CBSC MAC-based DCT filter [2407.08975]. The motivation for E-HTC is that these energy and area advantages were obtained with a MUX-based scaled addition mechanism that sacrifices computational accuracy.

## 2. Encoding model and arithmetic representation

In this line of work, “hybrid” refers to the joint use of pulse-rate and temporal data encoding. The original HTC description states that multiplication uses a hybrid approach, with one operand encoded as arrival time and the other as pulse count, while propagation uses temporal encoding [2407.08975]. This arrangement preserves reduced switch energy while expanding the range of arithmetic operations beyond what is typically associated with pure race-logic formulations.

E-HTC retains this temporal-bitstream representation and explicitly supports both unipolar and bipolar encodings. In unipolar mode, the data range is given as $[0,1]$ mapped to $0$ or $1$, which is used for unsigned data. In bipolar mode, the data range is $[-1,1]$, mapped using
$$
b = \frac{x+1}{2},
$$
which allows signed arithmetic [2509.22999].

The architectural flow described for E-HTC is: input encoding; multiplication; addition; scaling; and accumulation with output decoding. The inputs are temporally encoded as bitstreams, the multiplication is handled in the temporal domain, the bitstreams are then processed through deterministic summation rather than through a MUX, and the scaled sums are accumulated before final decoding [2509.22999]. This preserves the basic HTC arithmetic model while replacing the component identified as the dominant source of addition error.

## 3. Deterministic addition in E-HTC

The defining change in E-HTC is the substitution of deterministic adders for the MUX-based scaled addition used in HTC. The first of these blocks is the Exact Multiple-input Binary Accumulator (EMBA), which deterministically and precisely accumulates multiple input bitstreams and yields an exact binary sum in a single clock cycle. Its operation is expressed as
$$
S_{\mathrm{EMBA}}[t] = \sum_{i=1}^{N} x_i[t],
$$
where $x_i[t]$ is the bit from the $i$-th input at time $t$ and $S_{\mathrm{EMBA}}[t]$ is the binary sum at that time [2509.22999].

The second block is the Deterministic Threshold-based Scaled Adder (DTSA). DTSA performs scaled addition through thresholding rather than probabilistic MUX selection. For $K$ input streams, the output is
$$
y_{\mathrm{DTSA}}[t] =
\begin{cases}
1 & \text{if } \sum_{i=1}^{K} x_i[t] \geq \theta \\
0 & \text{otherwise,}
\end{cases}
$$
with the threshold $\theta$ chosen to achieve the required fraction or scaling [2509.22999].

These two blocks are integrated into a MAC unit that supports unipolar and bipolar encodings. The paper characterizes EMBA as error-free deterministic accumulation and DTSA as exact probability-to-bitstream scaling that minimizes the approximation error associated with random MUX selection [2509.22999]. In functional terms, E-HTC replaces stochastic or probabilistic summation with deterministic binary accumulation and threshold logic while keeping the low-switch temporal-bitstream computing style of HTC.

## 4. Implemented accelerators and reported metrics

The framework is demonstrated on a 4x4 MAC, a FIR filter, and an 8-point DCT/iDCT engine [2509.22999]. The reported results are summarized below.

| Implementation | Accuracy outcome | Area/power outcome |
|---|---|---|
| 4x4 MAC, unipolar | Matches CBSC RMSE; improves accuracy by 94% over MUX-based HTC | Reduces power and area by 23% and 7% vs MUX-based HTC; 64% and 74% vs CBSC |
| 4x4 MAC, bipolar | $2.09\%$ RMSE; 83% improvement over MUX-based HTC; approaches CBSC’s $1.40\%$ RMSE | Area and power savings of 28% and 43% vs MUX-based HTC; about 76% vs CBSC |
| FIR filter | PSNR gains of 3--5 dB; 30--45% RMSE reduction | Saves 13% power and 3% area |
| 8-point DCT/iDCT | PSNR gains of 10--13 dB; 70--75% RMSE reduction | Saves area and power over both MUX- and CBSC-based designs |

For the MAC, the unipolar result is framed as parity with the RMSE of a state-of-the-art CBSC MAC, combined with lower power and area. The bipolar result is framed as a substantial reduction in RMSE relative to MUX-based HTC while remaining close to CBSC accuracy and retaining lower area and power [2509.22999].

For the FIR and DCT/iDCT accelerators, the reported metrics are given in signal-fidelity terms rather than in direct classification-style error measures. The FIR experiments show PSNR gains of 3--5 dB, corresponding to 30--45% RMSE reduction, together with 13% power and 3% area savings. The DCT/iDCT engine shows larger PSNR gains of 10--13 dB, corresponding to 70--75% RMSE reduction, while also saving area and power over both MUX- and CBSC-based implementations [2509.22999].

## 5. Comparative interpretation and design implications

The central comparative axis is E-HTC versus MUX-based HTC. The original HTC framework established that temporal-pulse-rate hybridization could reduce power and area relative to Unary and CBSC designs, but its MUX-based scaled addition incurred an accuracy penalty [2407.08975]. E-HTC preserves the temporal encoding strategy while replacing the MUX with deterministic summation. This suggests that the principal accuracy bottleneck identified in HTC was the scaled-addition mechanism rather than the use of pulse-rate and temporal encoding as such.

The second comparative axis is E-HTC versus CBSC. The paper does not present E-HTC as a general replacement for CBSC under every condition; rather, it positions E-HTC as an implementation point with lower hardware cost and markedly improved accuracy relative to MUX-based HTC. In unipolar 4x4 MAC experiments, E-HTC matches the RMSE of the CBSC MAC, while in bipolar mode it approaches CBSC’s $1.40\%$ RMSE with lower area and power [2509.22999].

A further implication concerns scalability at the accelerator level. The paper states that EMBA and DTSA are embedded into a MAC structure and then demonstrated in FIR and DCT/iDCT engines. This suggests an architectural methodology in which deterministic summation is treated as a reusable primitive for temporal-bitstream datapaths rather than as a task-specific patch. The reported resource reductions for the accelerator-level implementations are smaller than the MAC-level reductions, but the accuracy gains remain pronounced, especially for DCT/iDCT [2509.22999].

## 6. Scope, terminology, and common sources of confusion

E-HTC belongs to the hardware-accelerator literature on temporal and pulse-rate encodings. In this usage, HTC denotes Hybrid Temporal Computing, and the “enhanced” qualifier refers to deterministic additions that improve accuracy relative to MUX-based scaled addition [2509.22999]. The term should not be conflated with another recent use of the acronym HTC in physical neural networks, where HTC denotes the Hotelling Trace Criterion, a task-conditioned measure of class separability defined as
$$
\mathrm{HTC} = \mathrm{tr}\left(\mathbf{S}_W^{-1}\mathbf{S}_B\right),
$$
and used to predict classification performance across optical fibres, vertical-cavity surface-emitting lasers, and coupled nonlinear oscillator networks [2606.31588].

A second source of confusion is the word “hybrid.” In E-HTC, “hybrid” refers to pulse-rate and temporal data encoding within arithmetic hardware. It does not refer to quantum-classical hybridization, nor to biologically inspired combinations of fast and slow memory systems. Those are distinct research programs with different architectures, targets, and evaluation criteria.

Taken in its own technical context, E-HTC is therefore best understood as an accuracy-oriented refinement of temporal-bitstream arithmetic for ultra-low-power MAC-centric accelerators. Its contribution is not the introduction of hybrid temporal encoding itself, which predates it, but the replacement of MUX-based scaled addition by deterministic accumulation and thresholding, together with empirical evidence that this substitution materially improves RMSE and PSNR while retaining the low area and power profile that motivated HTC in the first place [2509.22999].

Source: https://www.emergentmind.com/topics/accuracy-enhanced-hybrid-temporal-computing-e-htc