---
title: '6T-2R Bit-Cell: Hybrid SRAM-NVM Design'
url: https://www.emergentmind.com/topics/6t-2r-bit-cell
type: topic
---

# 6T-2R Bit-Cell: Hybrid SRAM-NVM Design

A 6T-2R bit-cell is a circuit primitive that combines six transistors with two resistive memory devices, typically RRAM, so that volatile CMOS state and programmable resistive state coexist within a compact cell. In the literature covered here, the term does not denote a single canonical topology. In "NVM-in-Cache: Repurposing Commodity 6T SRAM Cache into NVM Analog Processing-in-Memory Engine using a Novel Compute-on-Powerline Scheme" a conventional 6T SRAM cell in GF 22 nm FDSOI is augmented with two bipolar RRAM devices on isolated power lines, forming a compact 6T-2R bit-cell for compute-on-powerline PIM [2510.15904]. In "An RRAM-Based Implementation of a Template Matching Circuit for Low-Power Analogue Classification," the closely related 6T2R2M split-TXL ACAM cell uses two programmable TiOx-based RRAM devices as source-degeneration elements in hybrid inverters to define a two-sided analogue match window [2303.02651]. Across these realizations, the 6T-2R idea serves either simultaneous SRAM-plus-NVM storage and MAC accumulation or analogue threshold encoding and matchline-based classification.

## 1. Scope and architectural interpretations

The most direct interpretation of a 6T-2R bit-cell is a six-transistor CMOS cell with two resistive devices added without replacing the transistor-defined logic core. In the cache-oriented realization, the base cell is a conventional 6T SRAM cell with separated wordlines, bitlines BL/BLB, isolated vertical VDD rails, and horizontal VSS/GND; the two RRAM devices are inserted on the power lines, one per half of the cross-coupled latch [2510.15904]. In the analogue CAM realization, the six transistors are distributed across two hybrid inverters and an evaluation transmission gate, while the two RRAM devices appear as programmable degeneration resistors that set lower and upper template thresholds [2303.02651].

This distinction is important because the phrase “6T-2R” can otherwise be mistaken for a single standard cell. The SRAM-based implementation is a dual-use cache bit-cell that keeps standard 6T density and cache organization while adding non-volatile storage and PIM functionality. The ACAM implementation is a reconfigurable analogue comparator primitive in which the RRAMs encode a window rather than a digital bit. A plausible implication is that “6T-2R” is better understood as a design pattern—six active CMOS devices coupled to two programmable resistive devices—than as a single schematic archetype.

## 2. SRAM-derived 6T-2R integration for NVM-in-Cache

In the NVM-in-Cache architecture, the left RRAM, RLEFT, is in series between the left PMOS pull-up source node of Q and the left vertical power rail VDD1, and the right RRAM, RRIGHT, is in series between the right PMOS pull-up source node of QB and the right vertical power rail VDD2. WL1 gates the left NMOS access to BL and Q, WL2 gates the right NMOS access to BLB and QB, and VSS lines are shared with gated-GND control transistors driven by V1 and V2. The RRAMs are symmetrically placed on top of the PMOS source terminals and the VDD lines in BEOL above the cell, and separating WL1/WL2 does not incur area penalty; the reported result is “no bit-cell area overhead” while augmenting each 6T cell with 2R devices [2510.15904].

Hold, read, and write remain identical to conventional 6T SRAM. In hold mode, VDD1 = VDD2 = 0.8 V, WL1 = WL2 = 0, and V1 = V2 = 0.8 V. If Q = 1, PMOS M2 is ON and Q sits at VDD1; with VDD1 = Q = 0.8 V, no net current flows through RLEFT, so the cross-coupled latch is unperturbed regardless of RRAM state. The paper reports read latency 686 ps vs. 660 ps and row read energy 3.34 fJ vs. 2.23 fJ for a 512-bit row, indicating that read/write SNMs and latency are close to baseline. It also states that the RRAMs on the power rails do not inject extra disturb during normal SRAM reads/writes because no DC drop occurs when node equals VDD, and half-select immunity is preserved as access devices are controlled conventionally.

RRAM programming is explicitly separate from standard SRAM operation. The bipolar device model uses SET at +1.2 V and RESET at −1.2 V, with LRS ≈ 25 kΩ, HRS ≈ 1.2 MΩ, and programming pulse width ≈ 4 ns. HRS→LRS requires two cycles to program RLEFT and RRIGHT selectively; LRS→HRS is completed in a single cycle. Verify uses a single-cycle read at VDD1/VDD2 = 0.8 V and WL1/WL2 = 0.8 V, with BL/BLB current measured for 1 ns. A central constraint is that programming is destructive to the stored SRAM data, although the work argues that inference uses far more reads than writes, making the overhead acceptable.

## 3. Compute-on-powerline operation and mixed-signal MAC formation

The defining feature of the cache-oriented 6T-2R cell is compute-on-powerline PIM. PIM mode operates in two cycles, each 3.5 ns, exploiting cell symmetry. In cycle-1, computation occurs on the left half while the right half dynamically holds data; in cycle-2, the roles swap. During the sampling window, the bit-cell forms a controllable conductance path from the storage node to the VDD rail via RRAM and PMOS. When the binary input activation IA is asserted on WL1 or WL2, the cell contributes a current to the shared VDD rail proportional to the programmed RRAM conductance and the input drive. Currents from 128 cells in a column sum naturally on the low-impedance VDD1/VDD2 lines [2510.15904].

The governing equations are reported as
$$
y = \sum_{i=1}^{N} x_i w_i,
$$
$$
I_{\text{sum}} = \sum_{i=1}^{N} G_i V_i,
$$
with $G_i = 1/R_i$, and after calibration
$$
y \approx k \cdot I_{\text{sum}}.
$$
The weighted configuration circuit (WCC) time-multiplexes the VDD rails between nominal 0.8 V and PIM sampling bias, applies 8:4:2:1 weighting via NMOS current mirrors across eight VDD rails per 4-bit word, and uses a sample-and-hold capacitor to capture droop induced by $I_{\text{sum}}$. A 6-bit SAR ADC at 50 MHz with a strong-arm comparator and a 6-bit CDAC digitizes the result. Calibration expands code usage from an uncalibrated range of approximately 7–48 to the full 0–63 span using VREFP ≈ 820 mV and VREFN ≈ 260 mV, yielding monotonic mapping and near-linear response after inverse post-processing.

Weights are binary at the device level: HRS encodes “0” and LRS encodes “1.” A 4-bit weight is distributed across four columns per word, with both RLEFT and RRIGHT programmed to the same state to preserve latch symmetry. Inputs are also represented bit-serially: 4-bit activations are processed in four cycles per side, avoiding large DAC area and power. Effective MAC precision is therefore 4b × 4b per 128-row operation, with shift-and-add accumulation and signed subtraction performed outside the array. Data preservation during compute depends on the opposite half of the cell holding the latch state and on gated-GND sequencing that suppresses BL→GND DC paths while WL is asserted.

## 4. Analogue threshold encoding in the 6T2R2M split-TXL cell

The 6T2R2M split-TXL ACAM cell uses a different mapping of six transistors and two resistive devices. MP1/MN1 and MP2/MN2 form two source-degenerated hybrid inverters whose trip points are controlled by RM1/R1 and RM2/R2, respectively; M_PML and M_NML form an evaluation transmission gate between BL and ML. RM1 sets the lower bound of the match window, RM2 sets the upper bound, and the two additional static resistors R1 and R2 anchor the ratios and reduce the dynamic range required of the RRAMs [2303.02651].

Search proceeds by precharging BL to VDD and holding ML at GND, then broadcasting the analogue query voltage $V_{\text{in}}$ to all cells in the row. Each hybrid inverter digitizes the query at its programmed trip point. When $V_{\text{in}}$ is above the lower threshold and below the upper threshold, OUT_LO and OUT_HI bias both evaluation transistors into conduction, connecting BL to ML and injecting a packet of charge. Cells with in-window inputs contribute current, so ML rises toward VDD at a rate determined by the number of conducting cells and the effective transmission-gate resistances.

The paper gives the row-level formulation as
$$
I_{\text{cell}}(V_{\text{in}}, V_{\text{ML}}) \approx \frac{V_{\text{BL}} - V_{\text{ML}}}{R_{\text{cell}}(V_{\text{in}})},
$$
$$
I_{\text{ML}}(V_{\text{ML}}) = \sum_i m_i(V_{\text{in},i}) \frac{V_{\text{DD}} - V_{\text{ML}}}{R_{\text{cell},i}},
$$
and
$$
C_{\text{ML}} \frac{dV_{\text{ML}}}{dt} = I_{\text{ML}}(V_{\text{ML}}) - I_{\text{Leak}}(V_{\text{ML}}).
$$
With leakage approximated as $V_{\text{ML}}/R_{\text{Leak}}$, the first-order solution yields $V_{\infty}$, $\tau$, and a time-to-threshold decision $t_{\text{match}}$. The threshold positions satisfy qualitative dependencies
$$
V_{\text{TR,LO}} \approx F_1(RM1/R1, \beta_{P1}/\beta_{N1}, V_{DD}),
$$
$$
V_{\text{TR,HI}} \approx F_2(RM2/R2, \beta_{P2}/\beta_{N2}, V_{DD}),
$$
with match window $W \equiv V_{\text{TR,HI}} - V_{\text{TR,LO}}$.

Programming in the PCB demonstrator uses 100–500 μs pulses, with reads at 250 mV. The prototypes cover approximately 30 kΩ–8.6 MΩ, while the 180 nm simulations sweep RM1 and RM2 over 2.5–250 kΩ with R1 = R2 = 10 kΩ. The reported design rule is that the programmable conductances should traverse above and below the balancing resistors by approximately $10\times$ to span a wide threshold range with good sharpness, which the paper contrasts with prior designs that required approximately $50\times$ conductance ratio.

## 5. Quantitative performance and demonstrated workloads

For the cache-based 6T-2R cell, the sub-array is 128 × 512 1-bit cells, organized as a 128 × 128 4-bit word array, and 128 rows accumulate simultaneously on column VDD rails. The reported normalized throughput is 0.4 TOPS at VDD = 0.8 V, normalized to 1-bit, and the reported normalized energy efficiency is 491.78 TOPS/W. The paper further reports compute density ≈4.37 TOPS/mm², macro ≈0.1 mm², and energy per 1-bit MAC
$$
E_{\text{MAC}} = \frac{1}{491.78 \cdot 10^{12}} \approx 2.03 \text{ fJ/MAC}.
$$
ADC dominates latency at 50 MHz with approximately 160 ns per conversion; bit-serial operation gives approximately 640 ns PIM per side, with the two sides computed sequentially. In the ML demonstration, an IFM-reuse strategy maps ResNet-18 on CIFAR-10 using 4-bit weights, 4-bit activations, and 6-bit signed ADC output. The achieved accuracy is 91.27% after fine-tuning, compared with baseline 91.84%, 91.55% with ADC nonlinearity, and 91.27% with nonlinearity plus noise [2510.15904].

For the split-TXL ACAM cell, the IC-level estimate is approximately 60 pJ per classification event in a commercial 180 nm PDK at VDD = 1.8 V. Transient simulations use a 450 ps evaluation pulse after a 2.35 ns settle. Single-cell energies in Table 2 are tens of femtojoules, with hit energies 31–63 fJ and miss energies 4–41 fJ. The demonstrator uses a software threshold of 700 μA per matchline. Maximum window widths in the 180 nm simulations are 517 mV for the minimum configuration, 609 mV for the wide configuration, and 622 mV for the native configuration at 25°C; FF/SS corners shift these ranges, and Monte Carlo with 250 runs gives window-width standard deviations of approximately 17–23 mV depending on geometry [2303.02651].

These metrics illustrate two distinct operating points for 6T-2R-derived cells. One is a cache-compatible analog PIM macro whose performance is limited primarily by ADC bandwidth and mixed-signal periphery; the other is a low-power analogue classifier whose performance is tied to matchline charging dynamics, threshold-window sharpness, and device-ratio programmability.

## 6. Reliability, scaling limits, and trade-offs

The reliability envelope of the cache-based 6T-2R cell is shaped by RRAM variability, rail integrity, and converter overhead. The work reports monotonic weight-to-current behavior across SS/TT/FF corners, with mild nonlinearity in the FF corner because stronger transistor drive reduces effective voltage across the RRAM stack; calibration and task-aware fine-tuning are used to compensate. Scalability is limited by IR drop on VDD rails as the number of active rows increases, by line resistance and capacitance on VDD columns and WL/BL drivers, and by ADC bandwidth. The proposed mitigations are pre-settling, hierarchical VDD rails, short columns, tiling, local WCC, segmented columns, repeaters, and higher-speed or interleaved ADCs, including shared ADC via 3D integration. The paper also emphasizes that PIM compute does not corrupt SRAM content because of powerline-based decoupling and gated-GND sequencing, even though RRAM programming disturbs the SRAM data and must be followed by restoration if needed [2510.15904].

In the ACAM cell, the principal nonidealities are device-to-device and cycle-to-cycle variability, minor volatility and drift in TiOx devices, significant FF/SS corner dependence, and random small-range drift during sweeps. Temperature dependence from 25–37°C is described as minor, while corner dependence is substantial enough to affect both energy and window width. Retention and endurance are not quantified, and the demonstrator is characterized as program-once/read-many. The architecture avoids sneak paths typical of crossbars because it is not a passive crosspoint network, and low read biases minimize read disturb [2303.02651].

The trade-off space differs accordingly. Relative to pure SRAM PIM in charge or time domain, the cache-oriented 6T-2R cell preserves cache data during compute, adds non-volatile storage capacity, and avoids cache flush/reload, but latency and area are dominated by ADC and WCC. Relative to hybrid 6T-1R or 8T/10T SRAM PIM, it maintains 6T density and pitch. Relative to crossbar RRAM PIM, it avoids selector and sneak-path problems, and precision is governed by ADC and bit-serial protocol rather than crossbar SNR and IR issues. In the ACAM setting, the ratio-centric use of two RRAMs plus two static resistors reduces the required conductance span, sharpens threshold control, and supports current-mode matchline charging, but the attainable window remains sensitive to MOS sizing, process corner, and operating resistance regime. Together, these results suggest that the 6T-2R bit-cell is best understood as a compact mixed-memory primitive whose utility depends on how the two resistive devices are embedded: on SRAM power rails for compute-on-powerline PIM, or inside source-degenerated inverter branches for analogue threshold comparison.

Source: https://www.emergentmind.com/topics/6t-2r-bit-cell