---
title: '2T-nC FeRAM: Non-Volatile Memory & Logic'
url: https://www.emergentmind.com/topics/2t-nc-ferroelectric-ram-feram
type: topic
---

# 2T-nC FeRAM: Non-Volatile Memory & Logic

Searching arXiv for the specified paper and closely related ferroelectric-memory work to ground the article.
First, retrieving the main 2T-nC FeRAM paper by arXiv ID.
Searching for adjacent ferroelectric memory papers cited in the brief to contextualize architecture, readout modality, and complementary/vertical alternatives.
2T-nC ferroelectric RAM (FeRAM) is a ferroelectric-capacitor-based memory organization in which a cell contains two transistors and \(n\) ferroelectric capacitors, with data stored in the polarization state \(P_{FE}\) rather than as volatile charge. In the formulation reported in “Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation” [2509.17963], the architecture is notable not only as a non-volatile alternative to 1T-1C DRAM, but also as a substrate for single-cell logic-in-memory (LiM). Its defining property is a quasi-nondestructive readout (QNRO) mechanism whose inverted readout polarity can be exploited for NOT and, in a 2T-3C realization, for a single-cell MINORITY function that yields universal NAND and NOR logic. The same work further argues that vertical 3D integration can increase storage and computational density while preserving thermal viability under stacking [2509.17963].

## 1. Cell organization and memory state

In the reported organization, “2T-nC” denotes a memory cell built from two transistors and \(n\) ferroelectric capacitors. The two transistors are a write transistor \(T_W\) and a read transistor \(T_R\), while the capacitors are implemented as metal-ferroelectric-metal (MFM) capacitors, each capable of holding one stored polarization state. This organization differs from both 1T-1C DRAM and 1T-1C FeRAM because the write and read paths are decoupled rather than sharing a single access path [2509.17963].

The storage variable is the ferroelectric polarization \(P_{FE}\). Positive \(P_{FE}\) corresponds to one stored bit state, described in the source as bit ‘1’, while negative \(P_{FE}\) corresponds to the other stored state, bit ‘0’. Write is performed by applying controlled voltages on the write bit line (WBL) and write plate line (WPL) while enabling \(T_W\), thereby programming the target ferroelectric capacitor. The sequence is described as raising the WBL of the selected capacitor, activating the write word line (WWL) to turn on \(T_W\), connecting to WPL, and then applying controlled voltage pulses on WBL/WPL to set the target polarization. The same source also states that multiple capacitors within a single cell can be written simultaneously in one cycle [2509.17963].

The architectural consequence of this separation is central. Because \(T_W\) is dedicated to programming and \(T_R\) is dedicated to sensing, the cell can support both efficient storage and in-memory logic. A plausible implication is that the storage primitive is not merely a scaled ferroelectric replacement for a DRAM capacitor, but a read/write-decoupled computational memory element.

## 2. Quasi-nondestructive readout and inverting sense polarity

Read in 2T-nC FeRAM is organized around quasi-nondestructive readout rather than the destructive sensing associated with conventional ferroelectric capacitor read. During read, \(T_W\) is turned off, a small read voltage \(V_R\) is applied on WBL, a small voltage is applied to the read bit line (RBL), and the resulting current through \(T_R\), sensed at the read source line (RSL), depends on the stored polarization. The sensing chain is summarized as
\[
P_{FE} \rightarrow \Delta Q \rightarrow V_{int} \rightarrow I_{T_R} \rightarrow \text{SA output}.
\]
Here, \(\Delta Q\) is the read-induced switched charge, \(V_{int}\) is the internal voltage developed by that charge, and \(I_{T_R}\) is the current through the read transistor [2509.17963].

The asymmetry of the read response is expressed by
\[
\Delta Q_0 > \Delta Q_1.
\]
For positive \(P_{FE}\), identified with stored ‘1’, the read voltage causes only minimal switching, producing small switched charge \(\Delta Q_1\), low \(V_{int}\), and low current through \(T_R\). For negative \(P_{FE}\), identified with stored ‘0’, the read voltage causes greater switching, producing larger switched charge \(\Delta Q_0\), higher \(V_{int}\), and high current through \(T_R\). A sense amplifier compares this current against a reference and generates the output [2509.17963].

The distinctive feature is that the sensed output is inverting. Stored ‘0’ produces higher read current, and stored ‘1’ produces lower read current. The source explicitly treats this as the basis for NOT without external cell or peripheral modification. This sharply contrasts with DRAM LiM schemes in which NOT typically requires external modification such as the dual-contact cell in Ambit, and with 1T-1C FeRAM as described in the same source, where readout is characterized as destructive and non-inverting in the sense illustrated there [2509.17963].

The read is nonetheless only quasi-nondestructive, not fully nondestructive. A single read does not fully reverse the polarization, and the initial state remains “fairly intact,” so immediate write-back after every read is avoided. Repeated reads can still accumulate switching disturb and eventually require restoration. This distinction matters because it avoids the misconception that 2T-nC FeRAM eliminates read disturb entirely. It reduces restore burden substantially, but does not abolish it.

## 3. Single-cell logic-in-memory and universal computation

The LiM contribution of the reported 2T-nC FeRAM architecture is based on simultaneous activation of multiple ferroelectric capacitors inside one cell. In the demonstrated universal-logic example, the cell is a single 2T-3C unit containing one \(T_W\), one \(T_R\), and three MFM ferroelectric capacitors storing bits \(A\), \(B\), and \(C\). The work emphasizes that the universal logic is implemented within one cell, not by combining three separate memory cells [2509.17963].

The key logic primitive is Triple-Bit-Activation (TBA), in which the corresponding WBLs and RBL are activated simultaneously. The sensed output follows the MINORITY function:
\[
\text{MIN}(A,B,C)=\overline{C(A+B)+\overline{C}(A\cdot B)}.
\]
When \(C=0\), this reduces to
\[
\text{MIN}(A,B,0)=\overline{A\cdot B},
\]
which is NAND. When \(C=1\), it reduces to
\[
\text{MIN}(A,B,1)=\overline{A+B},
\]
which is NOR. Because NAND and NOR are universal, the single-cell MINORITY implementation yields a universal logic substrate [2509.17963].

The measured and simulated interpretation is threshold-based. The output current shows a monotonic opposite trend with the number of stored 1s and nearly linear separation across the patterns from ‘000’ to ‘111’. With the comparator reference placed between the currents for ‘001’ and ‘011’, the circuit distinguishes cases with at most one ‘1’ from cases with at least two ‘1’s. The logic can therefore be expressed as
\[
\text{MIN}(A,B,C)=1 \quad \text{iff} \quad A+B+C \le 1,
\]
and
\[
\text{MIN}(A,B,C)=0 \quad \text{iff} \quad A+B+C \ge 2.
\]
This is the complement of the 3-input MAJORITY function [2509.17963].

A common misconception is that ferroelectric LiM in this setting must, like DRAM bulk bitwise computing, rely on interactions among multiple rows or multiple cells. The reported 2T-nC FeRAM mechanism is materially different: logic is a function of multiple capacitors co-located within one cell, and inversion is intrinsic to the readout physics rather than imposed through an added circuit transformation.

## 4. Array primitives, performance, energy, and footprint

At the array level, the work contrasts DRAM and 2T-nC FeRAM through different command abstractions. DRAM bulk bitwise logic is described using AAP, or ACTIVATE–ACTIVATE–PRECHARGE. In the 2T-nC FeRAM organization, LiM uses ACP, or ACTIVATE–COPY–PRECHARGE, where ACTIVATE triggers the single-cell logic operation, specifically TBA; COPY transfers the sensed result from RSL to the destination through a tri-state buffer; and PRECHARGE resets the row for the next operation. A uniform latency of 1 cycle each is assumed for ACTIVATE, COPY, and PRECHARGE in the architecture model [2509.17963].

The distinction is tied to the read/write-path decoupling. Because RowClone is not directly applicable, COPY is implemented through a tri-state buffer. The reported advantage is that 2T-nC FeRAM performs logic in place and avoids the operand-copy overhead characteristic of DRAM-based LiM. The work attributes the resulting performance and energy gains not to lower per-command latency alone, but to elimination of DRAM refresh, avoidance of destructive-read copy overhead, and in-place single-cell logic execution [2509.17963].

The reported row-operation energies derived from SPICE simulations are \(22.6\ \text{nJ/row}\) for DRAM ACTIVATE, \(16.6\ \text{nJ/row}\) for 2T-nC FeRAM ACTIVATE, and approximately \(0.32\ \text{nJ/row}\) PRECHARGE energy for all technologies. Across eight simulated 1 GB data-intensive workloads—CRC8, XOR Cipher, Set Union, Set Intersection, Set Difference, Masked Initialization, Bitmap Index Query, and BNN Inference—using an 8 GB memory with 8 KB row size, the reported end-to-end result is 2\(\times\) higher performance and 2.5\(\times\) lower energy consumption than DRAM [2509.17963].

The footprint argument is linked to vertical integration. Using cited 28 nm data, a 2T-1C FeRAM unit cell occupies about \(30F^2\), with each ferroelectric capacitor accounting for \(1F^2\) and \(F=28\ \text{nm}\). A planar 2T-3C extension is estimated to occupy about \(\sim 90F^2\). By contrast, the proposed vertical stack is reported to achieve a footprint of about \(130 \times 130\ \text{nm}^2\), which the authors claim reduces footprint area per cell by about \(\sim 4.18\times\) [2509.17963]. This suggests that the logic density advantage is inseparable from the architectural decision to internalize multiple operands within a vertically realizable cell.

## 5. Vertical stacking and thermal operating envelope

The reported 3D extension places the read and write transistors in separate vertical positions and stacks the ferroelectric capacitors in the back-end-of-line (BEOL). In the proposed structure, a vertical string can hold multiple capacitors, for example a 2T-3C structure, so operands can be mapped onto vertically stacked ferroelectric capacitors without proportional lateral-area growth. Rows of such strings can then be activated together for high-bandwidth bitwise operations [2509.17963].

The system-level thermal study models a 3D SoC with an \((n+2)\)-layer stack of vertical 2T-nC FeRAM on top of a compute die. The figure-caption example cited in the source is a 5-layer 2 GB vertical 2T-nC FeRAM die stacked on a compute die represented by an Edge Google TPU with 28 W idle power, and with an additional 50% area overhead included for peripherals. Thermal behavior is analyzed using HotSpot under natural convection cooling with ambient temperature \(300\ \text{K}\). Under execution of the Bitmap Index Query workload, the steady-state peak temperature is reported as \(351.88\ \text{K}\), and the thermal profile is said to be consistent across all evaluated workloads [2509.17963].

Thermal viability is judged against measured and simulated ferroelectric behavior. The cited measurements show P–V loops from \(300\ \text{K}\) to \(390\ \text{K}\), nearly constant remanent polarization over that range, and decreasing coercive voltage as temperature increases. Simulated scaled-device P–V behavior is also described as retaining ferroelectric properties at operating temperatures. On that basis, the stacked 2T-nC FeRAM is presented as thermally viable and as preserving stable remanent polarization under the proposed 3D integration conditions [2509.17963].

The broader ferroelectric-memory context clarifies why this matters. Alternative non-destructive ferroelectric readout strategies exist, such as in-plane ferroelectric tunnel junctions that infer state through vertical tunneling current rather than switched polarization charge [1807.07562], and ultrathin HfO\(_2\)-based FTJs that use polarization-dependent electroresistance [2007.06182]. Those approaches demonstrate that destructive read is not intrinsic to ferroelectric memory as a category, but they are architecturally distinct from the capacitor-based 2T-nC organization. By contrast, the 2T-nC proposal retains a ferroelectric-capacitor memory model while reducing read destructiveness through QNRO and using that same mechanism for logic.

## 6. Experimental basis, limitations, and adjacent ferroelectric-memory concepts

The circuit-level simulations for 2T-nC FeRAM use Cadence Spectre with ASU 45 nm high-performance PTM transistor models and an MFM ferroelectric-capacitor model calibrated to Micron’s NVDRAM cell. The model is described as capturing ferroelectric behavior, device performance scaling, variation, stochastic switching, and domain-switching accumulation. This is important because the QNRO mechanism depends on partial switching and repeated-disturb behavior rather than on an idealized binary polarization reversal alone [2509.17963].

The experimental basis includes a fabricated 2T-nC FeRAM cell, SEM top-view imaging, transistor characterization, MFM capacitor characterization, and MINORITY-function validation. The transistor measurements report an on/off ratio of \(10^7\) and a subthreshold swing of \(110\ \text{mV/dec}\). The ferroelectric capacitor measurements report a P–V loop measured from \(300\ \text{K}\) to \(390\ \text{K}\) with voltage sweep from \(-3\ \text{V}\) to \(3\ \text{V}\), remanent polarization \(P_r=22.3\ \mu\text{C}/\text{cm}^2\), endurance to at least \(10^6\) cycles under \(\pm 3\ \text{V},\ 10\ \mu s\) bipolar pulses, and switching with pulse widths under \(300\ \text{ns}\) at \(\pm 3\ \text{V}\). For MINORITY validation, the authors write different values into three MFM capacitors and measure the read current at RBL, observing a monotonic opposite trend and near-perfect linearity from patterns ‘000’ through ‘111’ [2509.17963].

The limitations are explicit. Read is quasi-nondestructive rather than perfectly nondestructive, so cumulative switching disturb can eventually require restoration. Endurance of \(>10^6\) cycles is described as useful but not the upper bound of ferroelectric-memory endurance more broadly. The experimental demonstration uses relatively high voltages, up to \(\pm 3\ \text{V}\), and the manuscript does not provide a detailed sensing-margin formula or a full Monte Carlo failure analysis. Because read and write are separated, RowClone is not directly applicable and COPY must use a tri-state buffer. Practical realization of the 3D concept still requires BEOL ferroelectric integration, vertical transistor/capacitor stacking, fabrication co-optimization, and accommodation of peripheral overhead [2509.17963].

Adjacent work helps situate these tradeoffs without collapsing distinct device classes. Vertical complementary FeRAM, for example, uses two vertically stacked HZO capacitors programmed into complementary polarization states so that readout becomes a differential polarization summation; it is selector-free and transistor-free, and is therefore conceptually relevant to multi-capacitor signal boosting but not a 2T-nC topology [2604.15131]. BEOL-compatible 2-terminal ferroelectric analog memories based on WOx and HZO demonstrate another route to low-thermal-budget, crossbar-compatible ferroelectric storage, but with mixed ferroelectric and ionic-defect behavior and resistive rather than capacitor-based readout [2309.12061]. These neighboring directions underscore a broader point: 2T-nC FeRAM belongs to a family of ferroelectric memories concerned with non-volatility, read disturb, and density, yet its distinguishing contribution is that the read mechanism itself serves as a logic primitive within a transistor-accessed ferroelectric-capacitor cell [2509.17963].

Source: https://www.emergentmind.com/topics/2t-nc-ferroelectric-ram-feram