---
title: 112-Gbit/s PAM4 Transmission Overview
url: https://www.emergentmind.com/topics/112-gbit-s-pam4-transmission
type: topic
---

# 112-Gbit/s PAM4 Transmission Overview

Pulse amplitude modulation with four levels (PAM4) at 112 Gb/s (56 Gbaud) is a fundamental technology for next-generation optical interconnects and access networks, providing high spectral efficiency within stringent power and complexity constraints. 112-Gbit/s PAM4 transmission occupies a key regime for both short-reach (intra/inter-data center), passive optical network (PON), and fronthaul applications, requiring advanced electro-optic devices, digital signal processing (DSP), and equalization techniques to overcome hardware and channel impairments. The following exposition reviews leading architectures, device technologies, equalization methodologies, system performance, and future directions based on published experimental demonstrations and analysis.

## 1. Device Technologies and Modulator Architectures

PAM4 at 112 Gb/s has been realized using several modulator/transmitter types: silicon dual-drive Mach-Zehnder modulators (DD-MZM) [1811.11096], travelling-wave MZMs (TW-MZM) [1812.11081], silicon-organic hybrid (SOH) MZMs [2002.08176], directly-modulated long-wavelength VCSELs [1812.05536], and electro-absorption modulators (EAMs) [1801.10574]. Key parameters include electro-optic 3-dB bandwidth, drive voltage ($V_\pi$), insertion loss, and monolithic integration capability.

- **Silicon DD-MZM**: Fabricated in 0.13 μm silicon-on-insulator, with 2.5 mm arms, interleaved p-n junctions ($V_\pi$$\cdot$L$\approx1.73$ V$\cdot$cm), and 21 GHz EO bandwidth (at 2 V reverse bias) [1811.11096]. Supports SSB and DSB generation for PAM4 at 56–60 Gbaud.
- **TW-MZM**: 1.5 mm phase shifter, $V_\pi\approx4$ V, 21 GHz EO bandwidth at –1 V reverse bias, intentionally designed for near-50 Ω RF matching with on-chip terminations [1812.11081].
- **SOH-MZM**: Short slot waveguide (280–400 μm), $U_\pi L=0.41$ Vmm, insertion loss 0.7 dB/280 μm, electrical bandwidth ~40 GHz, with potential for >60 GHz with further optimization. Enables energy-efficient, ultra-compact modulators with low drive voltages compatible with CMOS SerDes [2002.08176].
- **DM-VCSEL**: 1.5 μm single-mode, 20 GHz small-signal modulation bandwidth at 7 mA bias. Utilized for SDM transmission (7-core MCF), limited by chirp-dispersion and bandwidth [1812.05536].
- **EAM**: ~25 GHz bandwidth, moderate chirp, used with 5G fronthaul testbeds [1801.10574].

The choice of modulation device determines the attainable bandwidth, linearity, extinction ratio, and integration with driver circuits.

## 2. Transmission Schemes and Link Architecture

PAM4 transmission at 56 Gbaud (112 Gb/s) is demonstrated across various distances and fiber/media:

- **Short-reach (1–2 km SSMF)**: Direct detection using DD-MZM or TW-MZM yields net bit rates $\approx$112 Gb/s post 7% FEC, with BER targets $<3.8\times10^{-3}$ [1812.11081]. Pre-emphasis, receiver equalization, and MLSD address ISI from finite bandwidth and fiber CD.
- **Long-reach (up to 80 km SSMF)**: Single-sideband (SSB) modulation with Kramers–Kronig (KK) direct detection eliminates CD-induced power fading, enabling record single-lane 112 Gb/s at 80 km with BER $2.46\times10^{-3}$ [1811.11096].
- **PON and SDM links**: 56 Gbaud PAM4 over multi-core fiber demonstrated 112 Gb/s/core at 1 km, with performance limited by VCSEL chirp and core-to-core variations [1812.05536]. 2.2 km PON links utilize EAMs or SOAs and require advanced equalization to meet BER and sensitivity targets [2411.19631, 2405.02609].
- **10 km Fronthaul**: EML-based transmitters with 10 km SSMF achieve FEC-threshold BERs with strong pre/post-equalization and DSP [1801.10574].

All architectures employ Nyquist or raised-cosine (RC) pulse shaping (roll-off $\leq0.1$) to minimize excess bandwidth, with transmission at $\sim56$ Gbaud for single-lane 112 Gb/s.

## 3. Digital Signal Processing and Equalization Techniques

Mitigating bandwidth constraints, chromatic dispersion, and device nonlinearity is critical in 112 Gb/s PAM4 systems.

- **Linear Equalization**: Feedforward equalizers (FFE) are implemented with 41–51 taps (typically decision-directed LMS or Sato algorithms) at the receiver, with transmitter-side pre-emphasis using 11 taps for EMLs/VCSELs [1801.10574, 1812.05536, 2405.02609].
  
- **Nonlinear and Advanced Equalization**: 
  - **Decision-Feedback Equalizers (DFE)**: Employed with directly-modulated VCSELs/EMLs; e.g., 7+7 taps achieve FEC threshold in most MCF cores [1812.05536].
  - **Maximum Likelihood Sequence Detection (MLSD)**: Two-tap post-filter plus MLSD enables ISI mitigation; especially necessary with SSB+KK architectures and limited modulator bandwidth, with Euclidean branch metrics [1811.11096, 1812.11081].
  - **Partial-Response PAM4 and MLSE**: Encoders implement channel memory ($1+D$), decoded by 4-state MLSE, slightly improving BER at the cost of DSP complexity [1801.10574].
  - **Machine Learning-based Equalizers**: 
    - **Kolmogorov–Arnold Networks (KAN)** and deep CNNs model nonlinearities (EAM/SOA), outperforming FIR and CNN baselines at a given computational budget [2411.19631]. For example, a 2-layer KAN achieves BER $<10^{-3}$ at ROP$\sim-4.6$ dBm using only 321 multiplications/symbol.
    - **Fourier Convolution-based Network (FConvNet)**: Leverages frequency-domain attention, multi-periodicity partitioning, and Inception-style convnets; achieves 2 dB sensitivity gain over 51-tap Sato equalizers and 1 dB over MLAs at BER $=5\times10^{-3}$, at only 1.7k multiplications/symbol [2405.02609].

| Equalizer Type           | Complexity (mults/sym) | BER ($\sim-2$ to $-4$ dBm ROP)             |
|-------------------------|------------------------|---------------------------------------------|
| 41-tap FFE              | 41–51                  | $10^{-3}$–$10^{-2}$                        |
| KAN-2                   | 321                    | $2.5\times10^{-4}$–$10^{-3}$               |
| CNN-2                   | 321                    | $7.0\times10^{-4}$–$10^{-3}$               |
| FConvNet (wl=64)        | 1,714                  | $3.2\times10^{-3}$ (2 dB gain over Sato)   |

Pre-equalization, post-filtering, and advanced sequence detection are all integral to optimizing 112 Gb/s PAM4 link performance.

## 4. System Performance and Transmission Metrics

Empirical performance of 112 Gb/s PAM4 depends on device bandwidth, channel impairment, DSP, and equalizer sophistication:

- **Short-range (1–2 km)**: BER $<3.8\times10^{-3}$ at ROP $-11.5$ dBm (1 km) and $-8.5$ dBm (2 km), corresponding to standard FEC thresholds [1812.11081].
- **Long-reach (80 km SSMF, SSB+KK)**: BER $2.46\times10^{-3}$ with net data rate $\sim$102 Gb/s (including FEC) [1811.11096].
- **PON/Fronthaul (2–10 km)**: BER $4 \times 10^{-3}$ at $-4$ dBm (10 km), with $\sim$4 dB margin over FEC threshold [1801.10574].
- **SDM/VCSEL**: At 56 Gbaud/1 km, five out of seven MCF cores achieve BER $<3.8\times10^{-3}$ using pre-equalization and DFE [1812.05536].

Optimal launch power, OSNR, and equalizer parameters are set per link; for 80 km links +8 dBm launch ($-9$ dBm Rx), OSNR penalty is 3–3.2 dB over short links [1811.11096].

## 5. Trade-Offs, Implementation, and Limitations

Major design trade-offs include:

- **Bandwidth-Limited Devices**: TW-MZM and SOH-MZM devices often have intrinsic $\sim$21–40 GHz bandwidth, requiring pre-emphasis, post-filtering, and MLSD. Aggressive DSP mitigates penalties but elevates complexity and power usage [1811.11096, 1812.11081, 2002.08176].
- **Equalization Complexity**: Linear FFE/DFE and MLSD suffice below 100 multiplications/symbol, while ML methods (KAN, CNN, FConvNet) achieve higher sensitivity at moderate complexity ($\sim$300–3k mults/sym) [2411.19631, 2405.02609].
- **Crosstalk (SDM/MCF)**: MCF cross-talk is $<{-45}$ dB over 100 km but core variation limits aggregate throughput [1812.05536].
- **SSB+KK Cost/Benefit**: SSB removes CD nulls but demands higher carrier-to-signal power ratio (CSPR$\sim$16.6 dB) and OSNR ($\sim$41.1 dB at 80 km), elevating transmitter power requirements [1811.11096].
- **Link Loss and FEC**: Tolerated loss budgets $>$20 dB (e.g., SOH-MZM), with 7% HD-FEC for <3.8e-3 BER, and net rates $\approx$104–112 Gb/s depending on configuration [2002.08176].

## 6. Future Directions and Research Opportunities

Further improvement of 112 Gb/s PAM4 systems will involve:

- **High-speed modulator technology**: Extension to $>$30–70 GHz EO bandwidth via optimized doping/segmented electrodes for both MZM and VCSELs, reducing the need for aggressive DSP [1811.11096, 2002.08176].
- **Integrated transmitter/driver circuits**: Co-packaged drivers and optical modulators to improve swing, reduce RF loss, and power consumption.
- **Advanced equalization**: Extension of KAN and FConvNet/DNN approaches to adaptively compensate for multi-dimensional impairment at low complexity, with on-chip implementation via LUTs or DSP slices [2411.19631, 2405.02609].
- **Higher-order modulation**: Exploration of PAM-6/8 and hybrid SSB-OFDM for spectral efficiency exceeding 112 Gb/s/lane [1811.11096].
- **Photonic integration**: Monolithic integration of laser, amplifier, and modulator for reduced coupling loss and overall cost.
- **Adaptive and nonlinear compensation**: Improved chirp management for VCSELs and robust nonlinear equalization for EAM/SOA-based links in high-loss or high-penalty environments.

These directions aim to meet stringent BER, power, complexity, and integration requirements for intra- and inter-data center interconnects, backhaul/fronthaul, and next-generation PON, supported by ongoing device and DSP innovation.

Source: https://www.emergentmind.com/topics/112-gbit-s-pam4-transmission