---
title: 100-GHz CMOS-Compatible RIS
url: https://www.emergentmind.com/topics/100-ghz-cmos-compatible-ris
type: topic
---

# 100-GHz CMOS-Compatible RIS

A 100-GHz CMOS-compatible reconfigurable intelligent surface (RIS) on silicon demonstrates monolithic, electronically steerable reflection at millimeter-wave (mmWave) frequencies, enabling low-loss, adaptive beamforming for 6G systems. This platform integrates phase-delay line engineering and VO₂-based phase-change switching within a foundry-compatible thin-film stack. Its principal innovations are a stacked slot/delay-line/VO₂ unit-cell architecture, loss-optimized for operation near 100 GHz, and programmable array-level phase profiles supporting micron-scale, on-die reflect-arrays. The design achieves a measured 180° phase shift with less than 1.2 dB loss and a 27.1 dB ON/OFF reflection contrast, validating the concept as a system-level building block for future on-chip wireless front-ends and adaptive metasurface controllers [2512.18854].

## 1. Unit Cell Structure and Phase-Delay Principle

The RIS unit cell is architected as a vertical multilayer stack optimized for CMOS process compatibility and mmWave performance.

- **Top Metal Slot**: A patterned copper strip-line forms an aperture with width $w_s = 187.5$ µm and length $l_s = 562.5$ µm. This functions as a frequency-selective capacitive window at $f_0 \approx 100$ GHz.

- **Phase-Delay Line Layer**: Below the slot, a meandering copper trace ($l_d = 400$ µm, $w_d = 30$ µm) carries embedded VO₂. The VO₂ segment bridges two copper fingers, enabling switchable path length.

- **Dielectric Stack**:
  - **SiO₂ Isolation**: PECVD SiO₂, $h_{SiO_2} = 15$ µm, $\epsilon_r \approx 3.9$, $\tan\delta \approx 0.002$.
  - **Ground Plane**: Fully metallized copper over high-resistivity silicon. Ground thickness is negligible compared to $\lambda_0/10$.
  - **Substrate**: High-resistivity silicon, $h_{Si} = 300$ µm, $\epsilon_r \approx 11.9$, $\tan\delta \approx 0.0002$.

The unit cell has a square footprint, $W_{sub}\times W_{sub} = 1.125$ mm $\times$ 1.125 mm.

### Phase-Control Mechanism

The phase switch exploits the insulator–metal transition of VO₂:

- **OFF State (VO₂-insulating)**: VO₂ $\epsilon_r \approx 9$, $\sigma \approx 10^3$ S/m. The absence of a conducting bridge forces current to detour, increasing the effective electrical path by $\Delta L \approx 400$ µm.
- **ON State (VO₂-metallic)**: VO₂ $\sigma \approx 10^5$ S/m increases conductivity, virtually shorting the delay line and minimizing path length.

The resulting phase difference at $f_0 = 100.75$ GHz is governed by
$$
\Delta\phi(\omega) = (2\pi f / c_0) \cdot \sqrt{\epsilon_{eff}} \cdot \Delta L
$$
where $\epsilon_{eff} \approx 6.5$. Substituting values yields a $\Delta\phi \approx 180^\circ$ shift between ON and OFF states.

| Layer/Material       | Parameter                     | Value / Property           |
|----------------------|------------------------------|---------------------------|
| Copper slot (top)    | $w_s, l_s$                   | 187.5 µm, 562.5 µm        |
| VO₂ (phase change)   | OFF: $\sigma\sim 10^3$ S/m   | ON: $\sigma\sim 10^5$ S/m |
| SiO₂ thickness, $\epsilon_r$| $h_{SiO_2}=15$ µm, $\epsilon_r\sim3.9$|                        |
| Substrate            | $h_{Si}=300$ µm, $\epsilon_r\sim 11.9$ |                  |

## 2. Scalable Array Layout and Beam Steering

A 60 × 60 element array forms an electronically steerable surface.

- **Element Pitch**: $d = 1.125$ mm ($\approx 0.375\,\lambda_0$ at 100 GHz).
- **Aperture**: $67.5$ mm total width ($\approx 22.5\,\lambda_0$).

### Phase-Gradient Programming

To steer a reflected beam to angle $\theta$ in the $x$–$z$ plane, a linear phase gradient is programmed:
$$
\Delta\phi = (2\pi/\lambda_0)\, d\, \sin\theta
$$
Phase profiles $\phi_{ij}$ for each element are computed and then quantized to two discrete states (1-bit): $\phi_1$ (VO₂ ON) and $\phi_2$ (VO₂ OFF).

### Simulated Array Patterns

- **Main Lobe**: At broadside ($\theta = 0^\circ$), array factor shows a single peak with half-power beamwidth $\approx 2.5^\circ$ (theoretical: $\approx 0.044$ rad).
- **Sidelobes**: First sidelobe level $\approx -13$ dB.
- **Scanned Beams**: For $\theta = \pm 20^\circ$, main-beam gain drops $<2$ dB, sidelobes remain below $-10$ dB.

## 3. Full-Wave Simulation and Performance Metrics

### Reflection and S-Parameters

Analytical and full-wave (HFSS) simulation at $f_0 = 100.75$ GHz (periodic boundary conditions, Floquet ports) indicate:

- **Magnitude**: Both ON and OFF states have $|\Gamma| > 0.88$ (reflection loss $<1.2$ dB).
- **Phase Difference**: $\angle\Gamma_{ON} - \angle\Gamma_{OFF} \approx 180^\circ$ ($\pm 5^\circ$).
- **Bandwidth**: Across $\pm 2$ GHz, phase difference remains within $180^\circ \pm 10^\circ$, and reflection above $-2$ dB.

### Loss and Efficiency

- **Insertion Loss per Cell**: $\approx 1.2$ dB total, with dielectric/conductor losses (SiO₂, Cu, VO₂) accounting for $\approx 0.6$ dB.
- **Aperture Efficiency**: Simulated between 55% and 60%.

| Parameter              | Simulated/Measured Value    | Conditions                  |
|------------------------|----------------------------|-----------------------------|
| Phase shift $\Delta\phi$ | $180^\circ \pm 5^\circ$   | $f_0 = 100.75$ GHz          |
| Reflection mag. $|\Gamma|$ | $>0.88$ ($<-1.2$ dB)    | Both VO₂ states             |
| Insertion loss         | 1.2 dB                     | Per unit cell               |
| ON/OFF measured contrast| 27.1 dB                   | Rx at $0^\circ$             |

## 4. Fabrication Workflow and CMOS Integration

The entire process flow employs methods compatible with back-end-of-line (BEOL) CMOS manufacturing.

1. **Substrate Preparation**: Start with a 300 µm high-resistivity silicon wafer.
2. **Ground Plane**: Sputter $\approx$200 nm copper.
3. **Meander Line Patterning**: Photolithography and lift-off for delay lines.
4. **SiO₂ Deposition**: PECVD, $h_{SiO_2} = 15$ µm; planarized if necessary.
5. **VO₂ Definition**: 100 nm VO₂ via sputtering or pulsed laser deposition (PLD), lithographically patterned as bridging element.
6. **Top Layer Patterning**: PECVD SiO₂ passivation (optional); photolithography/lift-off to define top copper slot layer (200 nm).

All deposition, patterning, and etch steps conform to industry-standard thin-film and photolithographic protocols.

### Experimental Validation

Measurement in a mmWave (up to 110 GHz) anechoic chamber uses:

- **Tx**: SFH-10 horn antenna at $12$ cm from array (far-field).
- **Rx**: Scanning horn measures reflected power at $–90^\circ$ to $+90^\circ$.

Measured specular reflection ($\theta=0^\circ$):

- **VO₂ OFF (insulating)**: $|\Gamma| \approx -20$ dB
- **VO₂ ON (metallic)**: $|\Gamma| \approx +7.1$ dB relative to OFF
- **ON/OFF Enhancement**: $27.1$ dB improvement

## 5. Capabilities and Implications for 6G Communications

The 100-GHz CMOS-compatible RIS achieves low-loss, high-contrast ($27.1$ dB) and 1-bit ($180^\circ$) phase-shift operation. The key system-level implications for 6G platforms include:

- **High-Throughput Links**: Enables spatially flexible, high-gain mmWave reflect-arrays for 6G backhaul and access.
- **On-Chip Integration**: CMOS-compatible processing supports direct integration with RF front-ends, control FPGAs/ASICs, and digital signal processors within a monolithic Si platform.
- **Fast Reconfiguration**: VO₂ switching in the sub-nanosecond to nanosecond regime supports beam reprogramming at MHz rates, compatible with rapidly changing channel conditions.
- **Phase Quantization Scalability**: Multi-bit phase tuning (2–3 bits) is readily implemented via multiple delay lines or cascaded VO₂ segments, with area as the main constraint.

However, challenges persist in precision thermal control of VO₂, scalable uniformity over full wafers, reliability over repeated switching cycles, and robust mmWave packaging under environmental stress. Nevertheless, the demonstrated fabrication flow, electrical performance, and measurement data establish a viable route toward dense, on-chip programmable metasurfaces for next-generation 6G adaptive communications [2512.18854].

Source: https://www.emergentmind.com/topics/100-ghz-cmos-compatible-ris